PCB Design

  • 6 Layers
  • One layer dedicated to a ground plane
  • One layer shared by 3.3V and 2.5V planes
  • Four layers dedicated to I/O routing
  • 5 mil traces / 20 mil power traces
  • 4x34 pin EHI ports and 1x40 pin USB Module port
  • 50 MHz Oscilator, One Pushbutton, and Three Status LED's

Test Fixture Design

  • Steel backing plate
  • Steel guide rods
  • Aluminum clamping plates
  • EHI Gasket
  • Steel collar with set screws
  • Replaceable TPS backing

Top Level Impact Detection Design

  • Describes the interface between physical hardware components which will be incorporated into the design.
  • The system will operate at 50MHz creating a detailed log file which will be transferred via USB to the PC to be sorted and viewed.

FPGA Internals Block Diagram

  • The FPGA will be designed with a 40-bit counter, allowing for up to ~6 hours between tests to provide unique time stamps for the impacts.
  • Data will be temporarily stored until transfer via USB in the FIFO (First In First Out) elastic buffer.

Updated GUI Prototype

  • Now written in C# to improve speed and to allow for better graphics
  • Still a work in Progress

GUI Prototype

  • Written using JavaScript and HTML
  • Displays breaks in the grid and highlights the intersections of these breaks
  • Later version will allow multiple samples to be displayed in sequence